IMPACT OF PROCESS VARIATIONS ON SOFT ERROR SENSITIVITY OF 32-NM VLSI CIRCUITS IN NEAR-THRESHOLD REGION By

نویسندگان

  • Lingbo Kou
  • William H. Robinson
  • Bharat L. Bhuva
چکیده

ACKNOWLEDGMENTS I would like to thank my advisor Dr. William H. Robinson first. I am thankful for the advice he gave me on my research as well as graduate study and the patient guidance. His advice on research and career are important for my future development. In addition, I would like to thank Dr. Bharat L. Bhuva for his thoughtful advice on my thesis work. I also want to thank the SAF-T group for the feedback and help on my research. Last, I would like to thank my family for the continuous support.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A new low power high reliability flip-flop robust against process variations

Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...

متن کامل

Designing and Evaluating Redundancy-based Soft Error Masking on a Continuum of Energy versus Robustness

Near-threshold computing is an effective strategy to reduce the power dissipation of deeply-scaled CMOS logic circuits. However, near-threshold strategies exacerbate the impact of delay variations on device performance and increase the susceptibility to soft errors due to narrow voltage margins. The objective of this work is to develop and assess design approaches that leverage tradeoffs betwee...

متن کامل

Comparative soft error evaluation of layout cells in FinFET technology

Keywords: Soft error Bulk FinFET MUSCA SEP3 VLSI design Supply voltage Soft error sensitivity a b s t r a c t This work presents a comparative soft error evaluation of logic gates in bulk FinFET technology from 65-down to 32-nm technology generations. Single Event Transients induced by radiations are modeled with the MUSCA SEP3 tool, which explicitly accounts for the layout and the electrical p...

متن کامل

On the Stability and Robustness of Non-Synchronous Circuits with Timing Loops

Among the most pressing issues in current deep submicron VLSI circuits are large parameter variations, primarily caused by process technology imperfections, that result in excessive delay variations, and continuously increasing soft error rates. The former seriously challenges the classic synchronous design paradigm, and coping with the latter requires suitable fault-tolerant architectures. In ...

متن کامل

Effect of Power Optimizations on Soft Error Rate

Due to technology scaling, devices are getting smaller, faster and operating at lower voltages. The reduced nodal capacitances and supply voltages coupled with more dense and larger chips are increasing soft errors and making them an important design constraint. As designers aggressively address the excessive power consumption problem that is considered as a major design limiter they need to be...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2014